1. Field of the Invention
The present invention relates in general to a method for distributing banks in a semiconductor memory device, in which individual cells are efficiently grouped into the banks, and more particularly to a bank distribution method for dividing each cell array vertically and horizontally into a plurality of banks and minimizing the length of a data bus to make a high-speed operation of the semiconductor memory device possible.
2. Description of the Prior Art
Generally, a group of cells individually accessed in a semiconductor memory device is called a bank. A very large scale integrated memory device requires a plurality of banks because the performance is enhanced by a bank-interleaved operation.
For example, a 16-Mbit (megabit) dynamic random access memory (DRAM) requires two banks, a 64-Mbit DRAM requires four banks, a 256-Mbit DRAM requires eight or sixteen banks, and a 1-Gbit (gigabit) DRAM requires thirty-two or more banks.
The distribution of banks is performed for the improvement in operation speed of a semiconductor memory device. This is due to the fact that the operation speed of the semiconductor memory device is much lower than that of a microprocessor, resulting in a degradation in the entire system performance. As a result, in order to meet high speed and high bandwidth requirements of the semiconductor memory device, a plurality of banks must be provided in the memory device. Such a conventional bank distribution method for the semiconductor memory device will hereinafter be described with reference to FIG. 1.
FIG. 1 is a view illustrating a distributed bank configuration of a conventional semiconductor memory device. As shown in this drawing, the conventional semiconductor memory device comprises a plurality of banks (for example, four banks 0-3), each of which is provided with two bank sections, or left and right bank sections, corresponding respectively to cell arrays. A column decoder is connected to each of the left and right bank sections, and a row decoder is positioned between the left and right bank sections and connected in common to them.
A data bus is provided with N (natural number) data bus lines for transferring data from the banks 0-3 to N input/output pads, respectively.
However, in the above-mentioned conventional semiconductor memory device, the length of the data bus is extremely long because it transfers data from all the banks 0-3 to the N input/output pads, resulting in a delay in data output. Such a data output delay makes a high-speed operation of the semiconductor memory device impossible.
Further, the bank implementation requires the same number of row decoders and row control signals as that of the banks, resulting in a significant increase in chip area.